A differential amplifier is a well-known circuit containing two inputs in which the output is proportional to the instantaneous differences between the two input signals. An ideal differential amplifier is designed to amplify the differences between the two input voltages while rejecting any signal elements they have in common. The amount of voltage common to both input lines of the differential amplifier is referred to as the common-mode voltage. The remainder is referred to as the differential voltage.
The common-mode voltage generally generates a common-mode base current which includes alternating current (ac) and direct current (dc) components. The dc component is referred to as the input bias current of the differential amplifier. The input bias current is undesirable and there are several prior art techniques to cancel as big a portion of it as possible.
FIG. 1 schematically illustrates a prior art scheme for input bias current cancellation of input transistors of a differential amplifier. An arrangement 100 is shown which includes positive and negative supply rails 110 and 120 respectively, NPN transistors Q1, Q2, Q3, Q4, Q5, Q6, Q10 and Q11, PNP transistors Q7, Q8, Q9, Q12 and Q13, and current sources IS1130 and IS2140. The transistors Q1 and Q2 form the input stage of the differential amplifier 150. It is understood that in one embodiment, the input stage includes two PNP transistors. In such an embodiment, the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q10 and Q11 include PNP transistors and the transistors Q7, Q8, Q9, Q12 and Q13 include NPN transistors.
In this description, the NPN and PNP transistors function in a manner that will be apparent to those of ordinary skill in the art. For this reason and to keep the description focused on the essence of the present invention, the design and operation of the individual transistors of the arrangement 100 are not mentioned in great detail. The NPN and PNP transistors are also referred to as the first and second conductivity type transistors respectively, or vice versa. Furthermore, the NPN and PNP transistors are also referred to as one conductivity type and opposite conductivity type transistors respectively, or vice versa.
Also, the terms rail, current source, tail current, input stage, PNP input stage, NPN input stage, base, emitter, collector, diode-connected transistor, bootstrap circuit and area of a transistor are used according to their ordinary meanings. Also, the term couple is used in its ordinary generally understood sense to mean to join two circuits, enabling signals to be transferred from one to another. The two circuits can be directly connected to each other or through an intervening element such as a third circuit. Also, the term electronic load is used in its ordinary generally understood sense to mean one or more resistors, one or more transistors, a current source coupled to one or more transistors, a current source coupled to one or more resistors, or a current source coupled to one or more resistors and one or more transistors. Finally, the terms sense and track are used in their ordinary generally understood sense to mean to detect current and to mimic the detected current respectively.
The arrangement 100 is used to cancel the input bias currents of the transistors Q1 and Q2. The transistors Q3 and Q4 are coupled to the transistors Q1 and Q2 respectively such that the base current of Q3 tracks the input bias current of Q1 and the base current of Q4 tracks the input bias current of Q2. The collector-emitter voltages (VCE) of the transistors Q1, Q2, Q3 and Q4 are the same and constant over the common mode range. Lateral transistors Q7 and Q8 are connected to the bases of the tracking transistors Q3 and Q4 respectively to current-mirror the base currents of Q3 and Q4. The mirrored currents are injected into the bases of the input transistors Q1 and Q2 to effectively cancel the input bias currents of these transistors Q1 and Q2.
The arrangement 100 can be referred to as a bootstrap circuit because the transistors Q9, Q10 and Q11 form a bootstrap loop 160. The bootstrap loop 160 is connected to the emitters of the transistors Q1, Q2, Q7 and Q8 and the bases of the transistors Q5 and Q6 such that the cancellation currents in the emitters of the transistors Q7 and Q8 will track the input bias currents of the transistors Q1 and Q2 when the common-mode input voltages fluctuate. The transistors Q10 and Q11 are diode-connected transistors.
The current source IS1130 ensures that the current flowing from the emitters of the transistors Q1 and Q2 into the current sink (negative rail) 120 is always constant.
The current source IS2140 ensures that the current in the loop 170 formed by the transistors Q9, Q10, Q11, Q12 and Q13 is always constant. The IS2140 current is mirrored to the transistor Q12 through the diode-connected transistor Q13. The collector current of the transistor Q12 is used to bias the bootstrap loop 160.
A disadvantage of the above circuit 100 is that the voltage drops caused by the transistors Q12, Q8, Q4 and Q2 limit the common-mode input voltage range over which the input bias currents are cancelled to being about 1.1 VDC away from the positive supply rail 110. In another words, the above arrangement 100 does not support input bias current cancellation for rail-to-rail differential amplifiers. The following numerical example illustrates the point.
In this example, the positive supply rail 110 voltage is +5 VDC and the negative supply rail 120 voltage is 0 VDC, the current gains (xcex2) of the NPN transistors Q1 and Q2 are 100, the input bias current before cancellation is 1 micro ampere (xcexcA), and the diode voltage drops across the active and saturated transistors are 0.7 VDC and 0.2 VDC respectively. For circuit analysis of the arrangement 100, the transistors Q2 and Q12 are saturated and the transistors Q4 and Q8 are active.
A circuit analysis of the arrangement 100 provides the IS1130 current at 202 xcexcA, the voltages of 4.8 VDC and 4.1 VDC at the transistor Q8 emitter and base respectively, 3.4 VDC at the transistor Q4 emitter, 3.2 VDC at the transistor Q2 emitter and 3.9 VDC at the common-mode input. The common-mode input voltage range over which the input bias currents are cancelled is limited to being about 1.1 VDC away from the positive supply rail 110.
It is understood that in a similar example in which the differential amplifier 150 includes a PNP transistors input stage, the common-mode input voltage range over which the input bias currents are cancelled is limited to being about 1.1 VDC away from the negative supply rail. For such an example, the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q10 and Q11 are PNP transistors and the transistors Q7, Q8, Q9, Q12 and Q13 are NPN transistors. Also, for such an example, the supply rail 110 is a negative supply rail and the supply rail 120 is a positive supply rail.
The present invention discloses a circuit to cancel an input bias current of a differential amplifier. In one embodiment, the circuit (200) includes an input stage (210) of the differential amplifier including first and second PNP transistors (Q21 and Q22). The collector of the first PNP transistor (Q21) is coupled to a first resistor (240), the collector of the second PNP transistor (Q22) is coupled to a second resistor (250), and the first and second resistors (210 and 250) are coupled to a negative supply rail. (230)
A tail current circuit (272) coupled to a positive supply rail (220) and the emitters of the first and second PNP transistors (Q21 and Q22) is disclosed. Also, a compensating current circuit (Q24) coupled to the tail current circuit (272) and the positive supply rail (220) is disclosed.
A third PNP transistor (Q25) is disclosed. The emitter of the third PNP transistor (Q25) is coupled to the compensating current circuit (Q24) and the collector of the third PNP transistor (Q25) is coupled to a third resistor (260) coupled to the negative supply rail (230). Also, a first diode-connected NPN transistor (Q26) is disclosed and the collector of the first diode-connected NPN transistor is coupled to the base of the third PNP transistor (Q25).
A first NPN transistor is disclosed (Q27). The base of the first NPN transistor (Q27) is coupled to the base of the first diode-connected NPN transistor (Q26), the emitter of the first NPN transistor (Q27) is coupled to the emitter of the first diode-connected NPN transistor (Q26) and the collector of the first NPN transistor (Q27) is coupled to the base of the second PNP transistor (Q22).
A second NPN transistor (Q28) is disclosed. The bases of the second and first NPN transistors (Q28 and Q27) are coupled to each other, the collector of the second NPN transistor (Q28) is coupled to the base of the first PNP transistor (Q21), and the emitters of the second and first NPN transistors (Q28 and Q27) are coupled to each other.
A bootstrap circuit (295) including third and fourth NPN transistors (Q30 and Q31), a first diode-connected PNP transistor (Q29), a second diode-connected NPN transistor (Q32) and a second current source (280) are disclosed. The emitters of the fourth NPN transistor (Q31) and the second diode-connected NPN transistor (Q32)are coupled to the negative supply rail (230), the collector of the second diode-connected NPN transistor (Q32) is coupled to the second current source (280) coupled to the positive supply rail (220), the bases of the fourth NPN transistor (Q31) and the second diode-connected NPN transistor (Q32) are coupled to each other, the collector of the fourth NPN transistor (Q31) is coupled to the collector of the first diode-connected PNP transistor (Q29), the emitters of the first diode-connected PNP transistor (Q29) and the third NPN transistor (Q30) are coupled to each other, and the collector of the third NPN transistor (Q30) is coupled to the positive supply rail (220).
The base of the third NPN transistor (Q30) is coupled to the emitters of the first and second PNP transistors (Q21 and Q22) and the tail current circuit (272), and the collector (or base) of the first diode-connected PNP transistor (Q29) is coupled to the emitters of the first and second NPN transistors (Q27 and Q28) and the emitter of the first diode-connected NPN transistor (Q26).
The tail current circuit (272) generates a bias current for the first and second PNP transistors (Q21 and Q22). The compensating current circuit (Q24) provides a current equal to the bias current to the third PNP transistor (Q25). The third PNP transistor (Q25) supplies the first diode-connected NPN transistor (Q26) with an input bias cancellation current. The first and second NPN transistors (Q27 and Q28) supply the bases of the second and first PNP transistors (Q22 and Q21) with the input bias cancellation current respectively. The bootstrap circuit (295) adjusts the input bias cancellation current responsive to a common mode voltage fluctuation. The circuit (200) can cancel the input bias current for common-mode voltages ranging up to within 0.2 volts (VDC) of the negative rail (230) voltage.
In another embodiment, the input stage (210A) of the differential amplifier includes two NPN transistors (Q21A and Q22A). In this embodiment, the integrated circuit (200A) can cancel the input bias current for common-mode voltages ranging up to within 0.2 volts (VDC) of the positive rail (220) voltage.